Recording and reproduction of an information signal in/from a track on a record carrier

ABSTRACT

Normally, in an MPEG recorder, during recording, a time stamp counter is locked to the program clock reference of the incoming stream by pulling the clock frequency of a controllable oscillator. During playback, the oscillator is left free running. Playback and recording situation lead to conflicting requirements. A solution is presented that does not have these conflicting requirements, namely by using an adder that adds an increment value to a count value in order to obtain the next count value. The time stamp values are derived from the count values. During recording, the value of the increment value is controllable, and during playback, the value of the increment value is fixed.

[0001] The invention relates to a recording apparatus recordingapparatus for recording an information signal in a track on a recordcarrier, the information signal comprising packets that may occurirregularly as a function of time in the serial datastream of theinformation signal, the apparatus comprising

[0002] input means for receiving the information signal,

[0003] time stamp generator means for generating time stamps having arelationship to the moment of occurrence of a packet comprised in theinformation signal received, the time stamp generator means beingadapted to generate subsequent cycles of count values in response to aclock signal, the time stamp generator means being adapted to derive atime stamp value in response to the detection of occurrence of a packetin said information signal received, a time stamp value for said packethaving a relationship to the count value at said moment of occurrence ofsaid packet,

[0004] combining means for combining a packet and its corresponding timestamp value so as to obtain a composite packet,

[0005] writing means for writing the composite packet in said track onthe record carrier, to a reproducing apparatus and to a recordingmethod.

[0006] A recording apparatus as defined in the opening paragraph isknown from WO 96/30905 (PHN 15260). The apparatus is adapted to recordan MPEG encoded information signal, such as a video signal, on a recordcarrier, such as a magnetic record carrier.

[0007] In prior art systems for recording MPEG Transport Streams it isnecessary to lock a local timestamp counter to the Program ClockReference of the incoming Transport Stream during recording. Thetimestamp counter is used to record the arrival time of an incomingTransport Stream packet in order to be able to reconstruct the originalpacket timing during playback. The timestamp counter must be locked tothe Program Clock of the incoming stream to make the recordingindependent of any frequency offset in the incoming Program ClockReference signal. In addition The Program Clock Reference of theincoming stream can be used as a timing reference for processes thatneed to lock to it (e.g. a drum in D-VHS).

[0008] During playback a free running clock is needed with a frequencyof 27 MHz and an accuracy of for instance +/−20 ppm. From this clock thepacket timing is reconstructed again and processes may be locked to thisclock.

[0009] The invention aims at providing an improved recording apparatus.The recording apparatus in accordance with the invention ischaracterized in that the time stamp generator means comprises:

[0010] variable increment value determining means for generating avariable increment value in response to a control signal,

[0011] adder means for adding the variable increment value to a countvalue in response to the clock signal so as to obtain a subsequent countvalue in a cycle of count values,

[0012] comparator means for comparing one or more program clockreference values comprised in packets in the information signal with oneor more time stamp values so as to derive the control signal therefrom.

[0013] The invention is based on the following recognition. Normally, inthe prior art recording apparatuses, the timestamp counter runs on alocal clock who's frequency is locked to the Program Clock Reference ofthe incoming stream. Any processes that need to be locked to the ProgramClock Reference can derive their timing from the locked clock. The localclock is derived from a Voltage Controlled Crystal Oscillator (VCXO)which is adjusted by a feedback control loop. During playback the VCXOis left free running (it gets a fixed control voltage) and its frequencyshould stay as close as possible to 27 MHz.

[0014] To do this two conflicting requirements are present for the VCXO.On the one hand, during recording, it needs to be pullable in order tolock to the incoming Program Clock Reference, while on the other hand itneeds to be stable and stay as close as possible to 27MHz duringplayback.

[0015] In accordance with the invention, a solution is presented thatenables the locking with a crystal that does not need to be pulled andonly has requirements for stability.

[0016] Instead of locking the frequency of the clock during recording,only the increment speed of one or more counters is adjusted (locked) tothe speed of the incoming Program Clock Reference. The state of thelocked counter(s) is used as a reference inside the recording system.

[0017] These and other aspects of the invention will be come apparentfrom the figure description in which

[0018]FIG. 1 shows an embodiment of the recording apparatus,

[0019]FIG. 2 shows an embodiment of a reproduction apparatus, and

[0020]FIG. 3 shows an embodiment of the time stamp value generator unit.

[0021] The apparatus of FIG. 1 has an input terminal 1 for receiving aserial datastream of MPEG packets. The input terminal 1 is coupled to afirst input of a signal combination unit 2, which has a second input forreceiving a time stamp value (TSV) that is included in a packet so as toobtain composite packets at its output. The output of the combining unit2 is coupled via a signal processing unit 4, in which a channel codingstep can be applied to the serial datastream of composite packets, to awrite unit 6, which write unit is adapted to write the processed serialdatastream of converted packets in a track on a record carrier 8, suchas a magnetic tape. In another embodiment, the processed serialdatastream of composite packets is recorded on a disk like recordcarrier 8 a, such as an optical disk. A packet detector unit 3 is alsoavailable for detecting the moment of occurrence of a packet and forgenerating a control signal in response to such detection. In responseto the control signal, the combining unit stores a time stamp value TSVin the packet detected.

[0022] A Program Clock Reference value extraction unit 10 is availablefor extracting the well known PCR values, defined in the MPEG standard,from those packets in the serial datastream received that comprise a PCRvalue. An output of the extraction unit 10 is coupled to a first inputof a comparator unit 12. A second input of the comparator unit 12receives the time stamp value TSV. A time stamp value generator unit 16is available for generating the time stamp values TSV. The generatorunit 16 comprises an adder unit 18 and an increment value generator unit20. The generator unit 20 supplies an increment value, denoted INC,which is supplied to a first input 22 of the adder unit 18. Further, amemory unit 24 is present for storing the output value available at theoutput 26 of the adder unit 18. The output 28 of the memory unit 24 iscoupled to a second input 30 of the adder unit 18. An oscillator unit 14is present for generating a clock signal with a frequency of 27 MHz andan accuracy of +/−30ppm. The memory unit 24 stores the output value ofthe adder unit 18 each time in response to a clock pulse supplied by theoscillator unit 14.

[0023] The increment value INC has an integer portion INT, expressed ina specified number of bits, such as P bits, and a fractional portionFRAC, also expressed in a specified number of bits, such as Q bits. Inan example, P=1 and Q=22. The adder unit 18 is adapted to add the P+Qbit increment value INC to an M+Q bit count value CV₁ that is suppliedto the inputs 22 and 30, respectively, and supplies the result, as thesubsequent count value CV₂ to its output 26. M equals 23, in the presentexample. Upon a clock signal, supplied by the oscillator unit 14, thecount value CV₂ is stored in the memory unit 24 and becomes therewiththe count value CV₁. The time stamp value TSV equals the integer portionINT of the count value CV₁, and only the M bits of the integer portionof CV₁ are supplied to the comparator unit 12 for comparison with thePCR value, more specifically with the M least significant bits of thePCR value, as well as to the signal combining unit 2, for inclusion in apacket.

[0024] CV₁ thus increments with each tick of the 27 MHz oscillator 14.However, the increment is not an integer equal to one, but a fractionalnumber close to 1.0 (for instance 1.0 +/−100 ppm). The increment INC isadjustable within the +/−100 ppm range (for instance in 256 or 512steps). Just as with the conventional approach, each time a PCR comesinto the system, it is compared against the TSV and if necessary theincrement INC of the count values is adjusted (instead of adjusting thefrequency of the oscillator, as in the prior art). Comparison resultsare low pass filtered in the comparator unit 12 to suppress theinfluence of PCR jitter in the incoming stream. In this way the TSV canbe locked to the incoming Program Clock.

[0025]FIG. 2 shows an apparatus for reproducing the composite MPEGpackets recorded on the record carrier 8 or 8a by the apparatus ofFIG. 1. The apparatus comprises a read unit 40 for reading the compositepackets from the record carrier. An output of the read unit 40 iscoupled to an input of a signal processing unit 42, which realizes asignal processing step on the signal read from the record carrierinverse to the signal processing carried out by the signal processingunit 4 of the recording apparatus. A series of composite packets appearat the output of the signal processing unit 42, which output is coupledto inputs of a buffer unit 44 and an extractor unit 46. The extractorunit 46 extracts the time stamp values TSV from the composite packetsand supplies the time stamp values to a first input of a comparator unit48. The packets, which may have retrieved the time stamp valuestherefrom are stored in the buffer unit 44. A reference time stampgenerator unit 50 is available for generating reference time stampvalues TSV_(r). Those reference time stamp values are supplied to asecond input of the comparator unit 48, for comparison with the timestamp values retrieved from the composite packets. Upon coincidencebetween a reference time stamp value and a time stamp value retrievedfrom a packet, a control signal is generated by the comparator unit 48on the line 52 and the packet from which the time stamp value wasretrieved is presented at the output 54 of the buffer unit 44 inresponse to the said control signal, such as for further processing.

[0026] The reference time stamp generator unit 50 comprises anoscillator unit 56 that generates a clock signal with a constantfrequency of 27 MHz. The generator unit 50 further comprises an adderunit 58 and an increment value generator unit 20 a. The generator unit20 asupplies an increment value, denoted INC, which is supplied to afirst input 62 of the adder unit 58. Further, a memory unit 64 ispresent for storing the output value available at the output 66 of theadder unit 58. The output 78 of the memory unit 64 is coupled to asecond input 70 of the adder unit 58. The oscillator unit 56 has anaccuracy of +/−30 ppm. The memory unit 64 stores the output value of theadder unit 58 each time in response to a clock pulse supplied by theoscillator unit 56.

[0027] The increment value INC has an integer portion INT, expressed ina specified number of bits, such as P bits, and a fractional portionFRAC, also expressed in a specified number of bits, such as Q bits. Inthe above given example, P=1 and Q=22. The adder unit 58 is adapted toadd the P+Q bit increment value INC to an M+Q bit count value CV₁ thatis supplied to the inputs 62 and 70, respectively, and supplies theresult, as the subsequent count value CV₂ to its output 66. Upon a clocksignal, supplied by the oscillator unit 56, the count value CV₂ isstored in the memory unit 64 and becomes therewith the count value CV₁.The reference time stamp value TSV_(r) equals the integer portion INT ofthe count value CV₁, and only the M bits of the integer portion of CV₁are supplied to the comparator unit 48 for comparison with the M-bit TSVvalue. M is again equal to 23.

[0028] CV₁ thus increments with each tick of the 27 MHz oscillator 56.The increment is a constant, preferably an integer equal to one. Just aswith the conventional approach, each time a TSV value is retrieved froma packet, it is compared against the reference value TSV_(r) and ifequality occurs, the packet in question is supplied to the output 54.

[0029] The increment value in the apparatus of FIG. 2 is thus fixed andrelates to the actual frequency of the oscillator 56. When theoscillator frequency is exactly 27 MHz, the increment value will beexactly 1. The apparatus may however account for a deviation of theactual frequency of the oscillator 56 from the required value of 27 MHz,by setting the increment value to a slightly higher value than 1, in thesituation where the frequency of the oscillator 56 is lower than 27 MHz,or by setting the increment value to a slightly higher value than 1,when it turns out that the frequency of the oscillator 56 is higher than27 MHz.

[0030] In an embodiment of the apparatus in accordance with theinvention which is capable of both recording and reproducing, theincrement value generator unit 20 a in the apparatus of FIG. 2 can, inaddition, be provided with a control signal input 82, and the apparatusmay then further be provided with the switch S₁ and the unit 80.

[0031] A control signal i,s generated on the line 27 to set theincrement value INC to a fixed value, such as the value 1. This controlsignal can be obtained from the unit 80, which is a preset controlsignal generating unit, that generates the control signal to preset theincrement value generator unit 20 a so that it generates the constantincrement value INC, such as the value 1. The switch S₁ could beincluded between the unit 80 and the unit 20a. The switch S₁ has aterminal a coupled to the control signal input 82 of the unit 20 a, aterminal c coupled to the output of the unit 80 and a terminal b coupledto the output of the comparator unit 12 of FIG. 1. In response to arec/pb control signal, the switch S₁ is set to its position a-b, whenthe apparatus is switched into the recording mode and is set to itsposition a-c when the apparatus is switched into its reproduction mode.In the reproduction mode, the increment value INC is constant,preferably equal to 1, and in the recording mode, the increment value iscontrollable by means of the control signal generated by the comparatorunit 12.

[0032]FIG. 3 shows a detailed structure of an embodiment of the timestamp value generation unit 16 and 50. The addition to be made in theadder unit 18 and 58 contains a ripple path of 22+9+14=45 bits (22 bitsin the fraction portion FRAC and 23 bits in the integer portion INT). A4-stage pipe-lined implementation of the adder unit is shown in FIG. 3.This has the advantage that the delay in the various components can bedecreased. by roughly a factor of 4, as will be explained later.

[0033]FIG. 3 shows four adders 82, 84, 86 and 88 that form the adderunit 18(58). The increment value generator unit 20(20 a) has three subunits 90 a, 90 b and 90 c. The sub unit 90 a generates the 11 leastsignificant bits of the fractional portion of the increment value,denoted FRAC[b₀, . . . b₁₀]. The sub unit 90 b generates the 10 mostsignificant bits of the fractional portion of the increment value,denoted FRAC[b₁₁, . . . b₂₁ ]. The sub unit 90 cgenerates one bit of theinteger portion of the increment value, denoted INT[b2 ₂]. The sub unitsgenerate in combination the increment value INC under the influence ofthe control signal supplied to them via the line 27. A delay 100, whichmay be in the form of a FIFO, and realizing a delay of T, which equalsone clock period of the 27 MHz oscillator, is provided between the subunit 90 b and the adder 84. A delay 102, which may also be in the formof a FIFO, and realizing a delay of 2T, is provided between the sub unit90 c and the adder 86.

[0034] The memory unit 24,64 has four sub units 92 a, 92 b, 92 c and 92d. The unit 92 ahas the 11 least significant bits of the fractionalportion of the count value CV₁ stored in it. The unit 92 b has the 10most significant bits of the fractional portion of the count value CV₁stored in it. The unit 92 c has the 9 least significant bits of theinteger portion of the count value CV₁ stored in it. The unit 92 d hasthe 14 most significant bits of the integer portion of the count valueCV₁ stored in it. The adder 82 adds the 11 least significant bits of thefractional portion of the increment value to the 11 least significantbits of the fractional portion of the count value CV₁. A carry-bit issupplied to the adder 84 via the carry-over control block 94 a. Theadder 84 adds the 10 most significant bits of the fractional portion ofthe increment value to the 10 most significant bits of the fractionalportion of the count value CV₁. A carry-bit is supplied to the adder 86via the carry-over control block 94 b. The adder 86 adds the bit of theinteger portion of the increment value to the 9 least significant bitsof the integer portion of the count value CV₁. A carry-bit is suppliedto the adder 88 via the carry-over control block 94 c.The adder 88 addsthe carry bit to the 14 most significant bits of the integer portion ofthe count value CV₁. Further, a delay 104, which may be in the form of aFIFO, and realizing a delay of T, which equals one clock period of the27 MHz oscillator, is coupled to the output of the sub unit 92 c. Adelay 106, realizing a delay of 2T, is coupled to the output of sub unit92 b,and a delay 108 realizing a delay of 3T is coupled to the output ofthe sub unit 92 a.

[0035] The 9-bit least significant portion of the integer portion of thecount value CV₁ runs from 0 to 299, in decimal notation. When the value299 is reached, a carry over control signal is generated via the block94 c. The 13-bit most significant portion of the integer portion of thecount value CV₁ runs from 0 to 16383, in decimal notation.

[0036] The increment value INC is thus a fractional number that isnormally very close to 1.0, in case it is locked to the program clock ofthe incoming stream. The deviation will then be in the range of +/−100ppm and depends on the frequency of the incoming program clock and thefrequency of the local oscillator frequency. The increment isrepresented by a 23 bit fixed-point number with one bit left of thedecimal point and 22 bits right of the decimal point. Bit b₂₂,represents the units, while bit b₀ represents the value 2^ (−22),roughly equal to 0.24 ppm. With the use of the increment value INC, theaverage increment per clock can be controlled in steps of 0.24 ppm.Nominally the increment is exactly 1.0, and by changing STC_INC it canbe made smaller or larger than 1.0.

[0037] The increment value generated by the increment value determiningmeans 20,20 a, is supplied in this embodiment to the adder unit 18,58 inthe following way. Upon a first clock pulse of the 27 MHz clock signal,the bits b₀ to b₁₀ of the fractional portion of the increment value,denoted INC(t=0), is supplied directly to the adder 82, whilst the bitsb₁₁, to b₂₁ are supplied to the delay 100 and the bit b₂₂ is supplied tothe delay 102.

[0038] Upon the second clock pulse of the 27 MHz clock signal, thefollowing operations are carried out:

[0039] (a) an adding operation is carried out in the adder 82, resultingin the bits b, to b,o of the fractional portion of the next count value,called CV₂(t=T), which bits are stored in the memory 92 a, and a carrybit is stored in the memory 94 a.

[0040] (b) further, the bits b₁₁ to b₂₁ of the increment value INC(0)are supplied to the output of the delay 100, and the bit b₂₂ of INC(0)is shifted one position in the delay 102.

[0041] (c) further, the bits b₀ to b₁₀ of the fractional portion of thenext increment value, denoted INC(T), is supplied directly to the adder82, whilst the bits b₁₁ to b₂, are supplied to the delay 100 and the bitb₂₂ is supplied to the delay 102.

[0042] Upon the third clock pulse of the 27 MHz clock signal, thefollowing operations are carried out:

[0043] (a) An adding operation is carried out in the adder 82, resultingin the bits b0 to b10 of the fractional portion of the next count value,called CV₂(2T), which bits are stored in the memory 92 a, and a carrybit is stored in the memory 94 a.

[0044] (b) An adding operation is carried out in the adder 84, resultingin the bits b₁₁ to b₂₁ of the fractional portion of the count valueCV₂(T), which bits are stored in the memory 92 b, and a carry bit isstored in the memory 94 b,

[0045] (c) Further, the bits b₁₁ to b₂₁, of the increment value INC(T)are supplied to the output of the delay 100, and

[0046] (d) the bits b₂₂ of INC(0) and INC(T) are shifted one position inthe delay 102, so that the bit b₂₂ of INC(0) is now supplied to theadder 86,

[0047] (e) and the bits b₀ to b₁₀ of the fractional portion of CV₂(T)are shifted one position in the delay 108.

[0048] (f) In addition, the bits of the next increment value INC(2T) aresupplied to the adder 82, the delay 100 and the delay 102.

[0049] Upon the fourth clock pulse of the 27 MHz clock signal, thefollowing operations are carried out:

[0050] (a) An addition is carried out in the adder 82, resulting in thebits b₀ to b₁₀ of the fractional portion of CV₂ (3T), which bits arestored in the memory 92 a, and a carry bit is stored in the memory 94 a,

[0051] (b) an adding operation is carried out in the adder 84, resultingin the bits b₁₁, to b₂₁ of the fractional portion of CV₂(2T), which bitsare stored in the memory 92 b, and a carry bit is stored in the memory94 b,

[0052] (c) an adding operation is carried out in the adder 86, resultingin the bits b₀ to b₈ of the integer portion of CV₂(T), which bits arestored in the memory 92 c, and a carry bit is stored in the memory 94 c,

[0053] (d) Further, the bits b₁₁ to b₂₁ of the increment value INC(2T)are supplied to the output of the delay 100, and

[0054] (e) the bits b₂₂ of INC (T) and INC(2T) are shifted one positionin the delay 102, so that the bit b₂₂ of INC(T) is now supplied to theadder 86,

[0055] (f) the bits b₀ to b₁₀ of the fractional portions of CV₂(T) andCV₂(2T) are shifted one position in the delay 108, and the bits b₁₁, tob₂₁ of the fractional portion of CV₂(T) are shifted one position in thedelay 106.

[0056] (g) In addition, the bits of the next increment value INC(3T) aresupplied to the adder 82, the delay 100 and the delay 102.

[0057] Upon the fifth clock pulse of the 27 MHZ clock signal, thefollowing operations are carried out:

[0058] (a) An addition is carried out in the adder 82, resulting in thebits b₀ to b₁₀ of the fractional portion of CV₂(4T), which bits arestored in the memory 92 a, and a carry bit is stored in the memory 94 a,

[0059] (b) an adding operation is carried out in the adder 84, resultingin the bits b₁₁ to b₂₁, of the fractional portion of CV₂(3T), which bitsare stored in the memory 92 b, and a carry bit is stored in the memory94 b,

[0060] (c) an adding operation is carried out in the adder 86, resultingin the bits b₀ to b₈ of the integer portion of CV₂(2T), which bits arestored in the memory 92 c, and a carry bit is stored in the memory 94 c,

[0061] (d) an adding operation is carried out in the adder 88, resultingin the bits b₉ to b₂₂ of the integer portion of CV₂(T), which bits arestored in the memory 92 d and thus become available at the out of thismemory 92 d.

[0062] (e) Further, the bits b₁₁ to b₂₁ of the increment value INC(3T)are supplied to the output of the delay 100, and

[0063] (f) the bits b₂₂ of INC (2T) and INC(3T) are shifted one positionin the delay 102, so that the bit b₂₂ of INC(2T) is now supplied to theadder 86,

[0064] (g) the bits b₀ to b₁₀of the fractional portions of CV₂(T),CV₂(2T) and CV₂(3T) are shifted one position in the delay 108, the bitsb₁₁, to b₂₁ of the fractional portions of CV₂(T) and CV₂(2T) are shiftedone position in the delay 106 and the bits b₀ to b₈ of the integerportion of CV₂(T) is shifted one position in the delay 104.

[0065] (h) In addition, the bits of the next increment value INC(4T) aresupplied to the adder 82, the delay 100 and the delay 102.

[0066] Now the complete 45-bit word CV₂(0) is available at the outputsof the delays 108,106,104 and the output of the memory 92 d.

[0067] Upon the next clock pulse, the complete 45-bit word CV(T) isavailable at those outputs. In this way, the processing delay as aresult of the addition has been decreased by roughly a factor of 4, forthe reason that the adder unit is divided into four adders with a carryover control and a delayed application of the increments to the adderunit.

[0068] Whilst the invention has been described with reference topreferred embodiments thereof, it is to be understood that these are notlimitative examples. Thus, various modification will become apparent tothose skilled in the art, without departing from the scope of theinvention, as defined by the claims. As an example, the time stampvalues could have been derived in a different way from the count valuesthan explained above, eg. by means of a rounding action on the countvalues. Further, the invention lies in each and every novel feature orcombination of features.

1. Recording apparatus for recording an information signal in a track ona record carrier, the information signal comprising packets that mayoccur irregularly as a function of time in the serial datastream of theinformation signal, the apparatus comprising input means for receivingthe information signal, time stamp generator means for generating timestamps having a relationship to the moment of occurrence of a packetcomprised in the information signal received, the time stamp generatormeans being adapted to generate subsequent cycles of count values inresponse to a clock signal, the time stamp generator means being adaptedto derive a time stamp value in response to the detection of occurrenceof a packet in said information signal received, a time stamp value forsaid packet having a relationship to the count value at said moment ofoccurrence of said packet, combining means for combining a packet andits corresponding time stamp value so as to obtain a composite packet,writing means for writing the composite packet in said track on therecord carrier, characterized in that the time stamp generator meanscomprises: variable increment value determining means for generating avariable increment value in response to a control signal, adder meansfor adding the variable increment value to a count value in response tothe clock signal so as to obtain a subsequent count value in a cycle ofcount values, comparator means for comparing one or more program clockreference values comprised in packets in the information signal with oneor more time stamp values so as to derive the control signal therefrom.2. Apparatus as claimed in claim 1, characterized in that the countvalue has an integer part and a fractional part, that the variableincrement value has an integer part and a fractional part and that thevariable increment value determining means is adapted to vary the valueof the integer part and the value of the fractional part of theincrement value in response to said control signal.
 3. Apparatus asclaimed in claim 1 or 2, characterized in that the variable incrementvalue determining means is adapted to vary the increment value around avalue of 1 in response to said control signal.
 4. Apparatus as claimedin claim 2, characterized in that the integer part of the count value isexpressed in M bits and forms the time stamp value, that the programclock reference value is expressed in N bits, where N and M are integersfor which hold N ≧M, and that the comparator means is adapted to comparethe M least significant bits of the N bit program clock reference valuewith the integer part of the count value for deriving the controlsignal.
 5. Apparatus as claimed in claim 1, 2, 3 or 4, characterized inthat the frequency of the clock signal is substantially constant. 6.Apparatus as claimed in anyone of the preceding claims, characterized inthat the apparatus is also adapted to reproduce the composite packetsfrom the track on the record carrier, the apparatus further comprisingread means for reading the composite packets from the record carrier,time stamp retrieval means for retrieving the time stamps from thecomposite packets, reference time stamp generator means for generatingreference time stamps, the reference time stamp generator means beingadapted to generate subsequent cycles of subsequent count values inresponse to a clock signal generated by oscillator means, the referencetime stamp values having a relationship with the count values,comparator means for comparing the time stamp values retrieved from apacket with the reference time stamp values generated by the referencetime stamp generator means and for generating a control signal inresponse to said comparison, presentation means for presenting saidpacket to an output in response to said control signal, characterized inthat the reference time stamp generator means comprises: increment valuegenerator means for generating a constant increment value, adder meansfor adding the increment value to a former count value in response tothe clock signal so as to obtain an actual count value.
 7. Apparatus forreproducing composite packets from the track on the record carrier, theapparatus comprising read means for reading the composite packets fromthe record carrier, time stamp retrieval means for retrieving the timestamps from the composite packets, reference time stamp generator meansfor generating reference time stamps, the reference time stamp generatormeans being adapted to generate subsequent cycles of subsequent countvalues in response to a clock signal generated by oscillator means, thereference time stamp values having a relationship with the count values,comparator means for comparing the time stamp values retrieved from apacket with the reference time stamp values generated by the referencetime stamp generator means and for generating a control signal inresponse to said comparison, presentation means for presenting saidpacket to an output in response to said control signal, characterized inthat the reference time stamp generator means comprises: increment valuegenerator means for generating a constant increment value, adder meansfor adding the increment value to a former count value in response tothe clock signal so as to obtain an actual count value.
 8. Apparatus asclaimed in claim 6 or 7, characterized in that the increment value isequal to
 1. 9. Method of recording an information signal in a track on arecord carrier, the information signal comprising packets that may occurirregularly as a function of time in the serial datastream of theinformation signal, the method comprising the steps of receiving theinformation signal, generating time stamps having a relationship to themoment of occurrence of a packet comprised in the information signalreceived, wherein subsequent cycles of count values are generated inresponse to a clock signal, a time stamp value being derived in responseto the detection of occurrence of a packet in said information signalreceived, a time stamp value for said packet having a relationship tothe count value at said moment of occurrence of said packet, combining apacket and its corresponding time stamp value so as to obtain acomposite packet, writing the composite packet in said track on therecord carrier, characterized in that the time stamp generator stepcomprises the substeps of: generating a variable increment value inresponse to a control signal, adding the variable increment value to acount value in response to the clock signal so as to obtain a subsequentcount value in a cycle of count values, comparing one or more programclock reference values comprised in packets in the information signalwith one or more time stamp values so as to derive the control signaltherefrom.